1. Field
This disclosure relates generally to memory, and more specifically, to a multiple block memory with complementary data path.
2. Related Art
In certain instances, memory is designed by combining several memory blocks to satisfy the requirements imposed by a system designer. These requirements may relate to constraints, such as the number of blocks, the number of I/O data paths, the number of rows per block, word length, process, voltage, temperature, and timing constraints. A memory designer may design memory blocks that may satisfy these constraints individually. When several memory blocks are combined to form a memory, however, these constraints may create timing problems. Specifically, for example, in such memories, data read from sense amplifiers corresponding to the memory blocks is latched in a global data hold latch. The global data hold latch is used to hold data indefinitely. The global data hold latch must tri-state just prior to the sense amplifier driver is activated. Global data hold latch must re-activate prior to the sense amplifier is tri-stated. These timing constraints are typically managed using global timing controls. Managing the timing relationship of the global data hold latch and the sense amplifier is difficult, however, across different requirements associated with the memory. Accordingly, there is a need for a multiple block memory with complementary data path.